Samsung S5PC100 User Manual page 209

Power Management
If TOP_LOGIC_ON_DIDLE = 1'b0, some IP modules in Top domain loses their states in F/F, and the other IP
modules keep their states in F/F after wakeup. Table 2.4-4 shows IP modules in Top domain that have retention
F/Fs, and those modules keep their states in F/F after wakeup.
However, IP modules in Top domain listed in Table 2.4-5 do not keep their states in F/F in DEEP-IDLE mode (Top
domain off), therefore the states of F/F should be saved into external memory, and be restored after wakeup.
Note that IP modules in Sub/Audio domains do not keep their states in F/F and SRAM when the power domains
become power-off.
In Deep-Idle mode OSC is always ON.
(1)
Retention Module
1) The state of SFR in Retention module is kept in top domain off.
To enter DEEP-IDLE mode:
1. Set CFG_STANDBYWFI field of PWR_CFG to 2'b01.
2. Set DEEP field register in CFG_DEEP_IDLE field of PWR_CFG to 1'b1.
3. Set PMU_INT_DISABLE bit of OTHERS register to 1'b1 to prevent interrupts from occurring while entering
DEEP-IDLE mode.
4. Execute Wait for Interrupt instruction (WFI).
PMU performs the following sequence on entering the DEEP-IDLE mode (TOP_LOGIC_ON_DIDLE = 1'b0). This
sequence is automatically done by hardware logic.
1. Completes all active bus transactions.
2. Completes all active memory controller transactions.
3. Initiates external DRAM to enter self-refresh mode (to preserve DRAM contents).
4. Mask clock input using internal signal in PMU.
5. Disables all PLLs except EPLL if Top domain is power-off.
6. Selectively disables OSCs except 32.768kHz.
To exit DEEP-IDLE mode:
1. Various types of wakeup sources are used. Wakeup sources referred in Section 5 WAKEUP SOURCES.
Then PMU performs the following sequence to exit DEEP-IDLE mode (TOP_LOGIC_ON_DIDLE = 1'b0).
1. Enables the OSC pads if disabled and waits for the OSC stabilization (around 1ms).
2. Unmasks clock input to clock-on blocks.
3. S/W sets system initialization including GPIO register setting since normal F/F lost information due to power-
gating.
4. S/W sets IO_RET_RELEASE bit of OTHERS register to 1'b1 to release retention for I/O pad.
5. S/W sets PLL initial setting (P/M/S value).
6. S/W sets EPLL_RET_RELEASE bit of OTHERS register to 1'b1 to release retention for EPLL input ports.
(Refer to 2.4.3.4.1 EPLL input retention and EPLL_RET_RELEASE)
7. S/W sets to Enable the PLLs and wait for locking (about 300us).
2.4-10
Table 2.4-4 IP Modules in Top Domain Having Retention F/Fs
SDMMC, USB Host 1.1, USB OTG link, CFCON, UART, I2S, SPI, PCM, AC97, IrDA,
System Timer
S5PC100 USER'S MANUAL (REV1.0)