Samsung S5PC100 User Manual page 983

SD/MMC CONTROLLER
CLKCON Bit
Reserved [7:4] Reserved
STBLEXTCLK [3]
ENSDCLK [2]
STBLINTCLK [1]
ENINTCLK [0]
8.12-48
External Clock Stable
This bit is set to 1 if SD Clock output is stable after writing to SD Clock
Enable in this register to 1. The SD Host Driver waits to issue command
to start until this bit is set to 1. (ROC)
'1' = Ready
'0' = Not Ready
SD Clock Enable
The Host Controller stops SDCLK if this bit is written to 0. SDCLK
Frequency Select changes if this bit is 0. Then, the Host Controller
maintains the same clock frequency until SDCLK is stopped (Stop at
SDCLK=0). If the Card Inserted in the Present State register is cleared,
this clears the bit (RW).
'1' = Enables
'0' = Disables
Internal Clock Stable
This bit is set to 1 if SD Clock is stable after writing to Internal Clock
Enable in this register to 1. The SD Host Driver waits to set SD Clock
Enable until this bit is set to 1.
Note: This is useful if PLL is used for a clock oscillator that requires
setup time. (ROC)
'1' = Ready
'0' = Not Ready
Internal Clock Enable
This bit is set to 0 if the Host Driver is not using the Host Controller or
the Host Controller awaits a wakeup interrupt. The Host Controller must
stop its internal clock to go at very low power state. Still, registers is able
to be read and written. Clock starts to oscillate when this bit is set to 1. If
clock oscillation is stable, the Host Controller can be set Internal Clock
Stable in this register to 1. This bit does not affect card detection. (RW)
'1' = Oscillate
'0' = Stop
Description
S5PC100 USER'S MANUAL (REV1.0)
Reset Value
0
0
0