Samsung S5PC100 User Manual page 498

S5PC100 USER'S MANUAL (REV1.0)
1.3 FUNCTIONAL DESCRIPTION
PC Card using memory mode has two distinct memory spaces namely: Attribute memory and Common memory.
The Attribute memory holds descriptive information and configuration registers (Card Information Structure CIS).
CIS informs about the type of card inserted and is used to configure system to recognize different types of cards
and load the correct drivers. This register has status change indication and reporting, 8/16 bits I/O mode selection,
interrupt pending status and so on.
The Common memory includes bulk storage of a memory card or device buffers in case of I/O cards. Common
memory accesses are 8-bit or 16-bit wide. The task file registers control the ATA disk drive. The task file registers
are mapped into common memory space (Task file registers have commands used to control all ATA/IDE drives).
The PC Card in I/O mode has transfers that are 8-bit or 16-bit wide. In PC Card I/O mode, the task file registers
are mapped into I/O address space. The value in card option register in attribute mode determines whether the
task file registers mapped to common memory or I/O space.
The PC card memory mode use nWE_CF (write enable strobe) and nOE_CF (output enable strobe) to access
memory locations. PC card distinguishes between attribute memory and common memory by the signal
nREG_CF. If nREG_CF is high, common memory is accessed. If this signal goes low, it access attribute memory.
The PC card I/O mode use nIOWR_CF and nIORD_CF to access I/O locations (Refer to Table 5.5-2).
Transaction Type
I/O Read
I/O Write
Attribute Memory Read
Attribute Memory Write
Common Memory Read
Common Memory Write
The PC card mode has two half-word (16-bits) write buffers and 4 half-word (16-bits) read buffers. The PC card
mode has 5 word-sized (32 bits) Special function Registers. Three timing configuration registers are available for
attribute memory, common memory and I/O interface. There is one status and control configuration register, and
one interrupt source and mask register.
The CFC is configured to True IDE mode, when the nOE_CF signal is grounded. The ATAPI controller is
compatible with the ATA/ATAPI-6 standard. This mode allows I/O operations to the task file and data registers. It
has access to one FIFO that is 16X32-bit. The ATAPI controller has internal DMA controller for data transfer
between ATA device and memory. The ATAPI controller has 32 word-sized (32-bits) Special Function Registers.
Table 5.5-1 Control Signaling Each Transaction Type
nIORD
0
1
1
1
1
1
nIOWR nOE
1 1
0 1
1 0
1 1
1 0
1 1
CF CONTROLLER
nWE nREG
1 0
1 0
1 0
0 0
1 1
0 1
5.5-3