Samsung S5PC100 User Manual page 977

SD/MMC CONTROLLER
9.10 HOST CONTROL REGISTER
Host Control Register
•
HOSTCTL0, R/W, Address = 0xED80_0028
•
HOSTCTL1, R/W, Address = 0xED90_0028
•
HOSTCTL2, R/W, Address = 0xEDA0_0028
This register contains the SD Command Argument.
HOSTCTL Bit
- Reserved [7]
- Reserved [6]
WIDE8 [5]
DMASEL [4:3] DMA Select
ENHIGHSPD [2]
WIDE4 [1]
- Reserved [0]
NOTE: Card Detect Pin Level does not simply reflect SDCD# pin, but selects from SDCD, DAT[3], or CDTestlvl depending
on CDSSigSel and SDCDSel values.
8.12-42
Reserved
This field should be fixed to LOW
Reserved
This field should be fixed to LOW
Extended Data Transfer Width (It is for MMC 8-bit card.)
'1' = 8-bit operation
'0' = Bit width is designated by the bit 1 (Data Transfer Width)
One of supported DMA modes can be selected. The host driver checks
support of DMA modes by referring the Capabilities register. Use of
selected DMA is determined by DMA Enable of the Transfer Mode
register.
00 = Selects SDMA
01 = Reserved
10 = Selects 32-bit Address ADMA2
11 = Selects 64-bit Address ADMA2 (Not supported)
High Speed Enable
This bit is optional. Before setting this bit, the Host Driver checks the High
Speed Support in the Capabilities register. If this bit is set to 0 (default),
the Host Controller outputs CMD line and DAT lines at the falling edge of
the SD Clock (up to 25MHz). If this bit is set to 1, the Host Controller
outputs CMD line and DAT lines at the rising edge of the SD Clock (up to
50MHz).
'1' = High Speed mode
'0' = Normal Speed mode
Data Transfer Width
This bit selects the data width of the Host Controller. The Host Driver sets
it to match the data width of the SD card.
'1' = 4-bit mode
'0' = 1-bit mode
Reserved
Description
S5PC100 USER'S MANUAL (REV1.0)
Reset Value
0
0
0
0
0
0
0