Samsung S5PC100 User Manual page 988

S5PC100 USER'S MANUAL (REV1.0)
NORINTSTS Bit
STACCS [9]
STACARDINT [8]
STACARDRE [7]
M
STACARDINS [6]
Read Wait interrupt status manually if BS = 0 (BS means 'Bus Status'
field 'Bus Suspend' register in the SDIO card specification)
Note: Read Wait operation procedure is started after 4-SDCLK from
the end of the block data read transfer.
CCS Interrupt Status (RW1C)
Command Complete Signal Interrupt Status bit is for CE-ATA interface
mode.
'0' = CCS Interrupt Occurred, '1' = CCS Interrupt Not Occurred
Card Interrupt
Writing this bit to 1 does not clear this bit. It is cleared by resetting the
SD card interrupt factor. In 1-bit mode, the Host Controller detects the
Card Interrupt without SD Clock to support wakeup. In 4-bit mode, the
card interrupt signal is sampled during the interrupt cycle, therefore
there are some sample delays between the interrupt signal from the
SD card and the interrupt to the Host System. It is necessary to define
how to handle this delay.
If this status is set and the Host Driver needs to start this interrupt
service, Card Interrupt Signal Enable in the Normal Interrupt Signal
Enable register must be set to 0 in order to clear the card interrupt
status latched in the Host Controller and to stop driving the interrupt
signal to the Host System. After completion of the card interrupt service
(It must reset interrupt factors in the SD card and the interrupt signal
may not be asserted), write to one clear to this register field(RW1C)
and set Card Interrupt Signal Enable to 1 to re-start sampling the
interrupt signal. The Card Interrupt Status Enable must remain set to
high. (RW1C) Note2,3
'1' = Generates Card Interrupt
'0' = No Card Interrupt
Card Removal
This status is set if the Card Inserted in the Present State register
changes from 1 to 0. If the Host Driver writes this bit to 1 to clear this
status, the status of the Card Inserted in the Present State register
must be confirmed. Because the card detect state may possibly be
changed if the Host Driver clear this bit and interrupt event may not be
generated. (RW1C)
'1' = Card removed
'0' = Card state stable or Debouncing
Card Insertion
This status is set if the Card Inserted in the Present State register
changes from 0 to 1. If the Host Driver writes this bit to 1 to clear this
status, the status of the Card Inserted in the Present State register
must be confirmed. Because the card detect state may possibly be
changed if the Host Driver clear this bit and interrupt event may not be
generated. (RW1C)
'1' = Card inserted
'0' = Card state stable or Debouncing
Description
SD/MMC CONTROLLER
Reset Value
0
0
0
0
8.12-53