Samsung S5PC100 User Manual page 385

DRAM CONTROLLER
1.2 BLOCK DIAGRAM
Low Power
AXI Low Power
Channel Manager
Control
Queue
(8/16
entries )
Bus Interface Block
Write Data
AXI
64bit
Buffer
Slave
AXI Channel
Interface
(32 depth)
Read Data
FIFO
(32 depth)
Functional
APB
Interface
Registers
Figure 5.1-1 shows the overall block diagram of the controller. The block diagram shows the bus interface block,
scheduler block, and memory interface block, which connects and interfaces with the SEC DDR PHY.
The bus interface block saves the bus transactions for memory access that come from the AXI slave port to the
command queue. Additionally it saves the write data to the write buffer or sends the read data to the Master via
the AXI bus. It also acts as a read FIFO if AXI Master is not ready and has an APB interface for special function
registers/ direct commands and an AXI low power channel interface.
The Scheduler block uses the memory bank Finite State Machine (FSM) information to arbitrate the bus
transactions in the command queues and transforms the commands into a memory command type, which is sent
to the Memory interface block. It also controls the write and read data flow between the memory and the AXI bus.
The Memory interface block updates each memory bank state according to the memory command coming from
the scheduler and sends the bank state back to the scheduler. It creates a memory command depending on the
memory latency and sends the command to the SEC DDR PHY via the PHY interface.
5.1-2
Bank FSM information
Queue
Arbiter
Final
Arbiter
AREF
Cmd
Direct
Cmd
Scheduler Block
Data
Control
Timing & configuration information
Figure 5.1-1 Overall Block Diagram
S5PC100 USER'S MANUAL (REV1.0)
Bank0
FSM
S0
S1 S2
PHY
I/F
Latency Control
Memory Interface Block
DLL
SEC
32 bit DDR / DDR 2 /
DDR
LPDDR / LPDDR 2
PHY