Samsung S5PC100 User Manual page 190

CLOCK CONTROLLER
CLKOUT frequency = CLKIN (selected by CLKSEL) frequency / (DIVVAL+1)
10.5 CLOCK GATING CONTROL REGISTER
The following three registers controls clock disable/ enable operation.
10.5.1 Control HCLKD0 / PCLKD0 Clock Gating 0 (System1) (CLK_GATE_D0_0, R/W, Address =
0xE010_0500)
D0 domain system1 clock gating
CLK_GATE_D0_0
Reserved
CLK_CSSYS
CLK_SECSS
CLK_G2D
CLK_MDMA
CLK_CFCON
CLK_TZIC
CLK_INTC
10.5.2 Control HCLKD0 / PCLKD0 Clock Gating 1 (Memory) (CLK_GATE_D0_1, R/W, Address =
0xE010_0504)
D0 domain memory clock gating
CLK_GATE_D0_1
Reserved
CLK_EBI
CLK_INTMEM
CLK_NFCON
CLK_ONENANDC
CLK_SROMC
CLK_DMC
2.3-40
Figure 2.3-15 CLKOUT Waveform with DCLK Divider
Bit
[31 : 7] Reserved
[6] Gating HCLK & PCLK for CSSYS (0: Mask, 1: Pass)
[5] Gating HCLK (0: Mask, 1: Pass)
[4] Gating HCLK for G2D (0: Mask, 1: Pass)
[3] Gating HCLK & PCLKEN for MDMA (0: Mask, 1: Pass)
[2] Gating HCLK for CFCON (0: Mask, 1: Pass)
Gating HCLK for trust interrupt controller
[1]
(0: Mask, 1: Pass)
Gating HCLK for vectored interrupt controller
[0]
(0: Mask, 1: Pass)
Bit
[31 : 6] Reserved
[5] Gating HCLK for EBI (0: Mask, 1: Pass)
[4] Gating HCLK for INTMEM (0: Mask, 1: Pass)
[3] Gating HCLK for NFCON (0: Mask, 1: Pass)
[2] Gating HCLK for ONENANDC (0: Mask, 1: Pass)
[1] Gating HCLK for SROMC (0: Mask, 1: Pass)
[0] Gating HCLK & PCLK for DMC0 (0: Mask, 1: Pass)
S5PC100 USER'S MANUAL (REV1.0)
Description
Description
Reset Value
0
1
1
1
1
1
1
1
Reset Value
0
1
1
1
1
1
1