Samsung S5PC100 User Manual page 715

CCAN
CANn_STS Bit
6.2.3 Error Counter
•
CAN0_ERR, R/W, Address = 0xEC70_0008
•
CAN1_ERR, R/W, Address = 0xEC80_0008
CANn_ERR Bit
RP [15]
REC6-0 [14:8]
TEC7-0 [7:0]
8. 5-18
100 = Bit1Error : During the transmission of a message (with
the exception of the arbitration field), the device wanted to
send a recessive level (bit of logical value '1'), but the
monitored bus value was dominant
101 = Bit0Error : During the transmission of a message (of
acknowledge bit, or active error flag, or overload flag), the
device wanted to send a dominant level (data or identifier bit
logical value '0'), but the monitored Bus value was recessive.
During busoff recovery this status is set each time after a
sequence of 11 recessive bits has been monitored. This
enables the CPU to monitor the proceeding of the busoff
recovery sequence (indicating the bus is not stuck at dominant
or continuously disturbed).
110 = CRCError: The CRC check sum is incorrect in the
message received. The CRC received for an incoming
message does not match with the calculated CRC for the
received data
111 = unused : If the LEC show the value '7', no CAN bus
event was detected since the CPU wrote this value to the LEC.
Receive Error Passive
1 = The Receive Error Counter has reached the error passive
level as defined in the CAN Specification
0 = The Receive Error Counter is below the error passive level
Receive Error Counter
Actual state of the Receive Error Counter. Values between 0
and 127
Transmit Error Counter
Actual state of the Transmit Error Counter. Values between 0
and 255
Description
Description
S5PC100 USER'S MANUAL (REV1.0)
R/W Reset Value
R/W Reset Value
R
R
R
0
0
0