Samsung S5PC100 User Manual page 354

ASYNC BRIDGE S5PC100 USER'S MANUAL (REV1.0)
Second, the big bubble between the write address channel and the write data channel should be investigated.
According to the AXI bus specification, the master issues the data of write transactions in the same order in which
it issues the transaction addresses. Therefore, If first arbitrated address channel's master is slower than the
second arbitrated address channel's master, the second arbitrated master should wait for all write data
transaction of slow master, although the second master can finish transaction of write data before first master's
starting of write data transaction. This is a big bubble.
The bubble generation mechanism and its solution are depicted in Figure 3.4-10. The basic idea is very simple.
The AWVALID assertion of slave part of Async Bridge is delayed as like delaying WREADY in first write
enhancement scheme.
Figure 3.4-10 Big Bubble Between AW Channel and W Channel and its Solution in Async Bridge
The delay cycle of AW channel and W channel depends on both the clock speed rate of fast and slow clock
domain and the burst size of transaction. Table 3.4-1 shows the required delay cycle for various burst transactions
and the fast and slow clock rate. For example, if the D0 clock speed is 166MHz, and the D1 clock speed is
133MHz, the Async_index should be set as "2" to enhance write performance of Async Bridge. The Async Bridge
automatically delays the AW channel and W channel to appropriate cycle for burst size of transactions.
3.4-12