Samsung S5PC100 User Manual page 179

S5PC100 USER'S MANUAL (REV1.0)
10.1.2 Control PLL Output Frequency for APLL (APLL_CON, R/W, Address = 0xE010_0100)
PLL_CON register controls the operation of each PLL. If ENABLE bit is set, the corresponding PLL generates
output after PLL locking period. The output frequency of PLL is controlled by the MDIV, PDIV, and SDIV values.
APLL_CON
ENABLE
LOCKED
Reserved
MDIV
Reserved
PDIV
Reserved
SDIV
The reset value of APLL_CON generates 400MHz output clock respectively, if the input clock frequency is 12MHz.
NOTE:
The output frequency is calculated by the following equation:
F = MDIV X F / (PDIV X 2
OUT IN
where, MDIV, PDIV, SDIV for APLL and MPLL must meet the following conditions :
PDIV: 1 ≤ PDIV ≤ 63
MDIV: 64 ≤ MDIV ≤ 1023
SDIV: 0 ≤ SDIV ≤ 5
/ PDIV): 3MHz ≤ F
F (=F
ref IN
/ PDIV): 1000MHz ≤ F
F (=MDIV X F
VCO IN
: 50MHz ≤ F
F
OUT VCO
Ex) For FOUT=500MHz, P=3, M=500, S=2
Bit
[31] PLL enable control (0: Disables, 1: Enables)
PLL is locked after locking time (locking time is set at
[30]
PLL_LOCK SFR)
[29:26] Reserved
[25:16] PLL M divide value
[15:14] Reserved
[13:8] PLL P divide value
[7:3] Reserved
[2:0] PLL S divide value
SDIV
)
≤ 6MHz
ref
≤ 2000MHz
VCO
≤ 2000MHz
Description
CLOCK CONTROLLER
Reset Value
0
0
0
0x190
0
0x3
0
0x2
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