Samsung S5PC100 User Manual page 695

IRDA
6.7 IRDA FIFO CONTROL REGISTER(IRDA_FCR, R/W, ADDRESS = 0XEC60_0018)
IrDA _FCR
Rx FIFO Trigger [7:6]
Level Select
FIFO Size Select
TX FIFO Clear
Notification
RX FIFO CLEAR
NOTIFICATION
Tx FIFO Reset
Rx FIFO Reset
FIFO Enable
8.4-16
Bit
Receiver FIFO trigger level selection.
Bit 7
0
0
1
1
[5] Must set to '1', to use 64 bytes TX and RX FIFO.
[4] This bit will be activated if the FIFO clear is over. This bit is cleared
by the CPU reads this register.
[3] This bit will be activated if the FIFO clear is over. This bit is cleared
by the CPU reads this register.
[2] TX FIFO reset. If set to '1', bit 2 clears all bytes in the transmitter
FIFO and reset its counter to '0'. A '1' written to bit 2 is self-clearing.
[1] RX FIFO reset. If set to '1', bit 1 clears all bytes in the receiver FIFO
and reset its counter to '0'. A '1' written to bit 1 is self clearing.
[0] FIFO enable. If set to '1', bit 0 enables both the transmitter and
receiver FIFOs. Bit 0 must be a '1' when setting other IrDA_FCR
bits. Changing bit 0 clears the FIFO.
Description
Bit 6 64-byte RX FIFO
0 01
1 16
0 32
1 56
S5PC100 USER'S MANUAL (REV1.0)
Initial State
00
0
0
0
0
0
0