Samsung S5PC100 User Manual page 873

USB2.0 HS OTG
8.2.10 Core Interrupt Register (GINTSTS, R/W, Address = 0xED20_0014)
This register interrupts the application for system-level events in the current mode of operation (Device mode or
Host mode).
GINTSTS Bit
WkUpInt [31]
SessReqInt [30]
DisconnInt [29]
ConIDSts [28]
Chng
Reserved [27]
PTxFEmp [26]
HChInt [25]
PrtInt [24]
Reserved [23]
8.10 -30
Resume/ Remote Wakeup Detected Interrupt
In Device mode, this interrupt is asserted if a resume is detected
on the USB. In Host mode, this interrupt is asserted if a remote
wakeup is detected on the USB.
Session Request/ New Session Detected Interrupt
In Host mode, this interrupt is asserted if a session request is
detected from the device. In Device mode, this interrupt is
asserted if the b_valid signal goes high.
Disconnect Detected Interrupt
Asserted when a device disconnect is detected.
Connector ID Status Change
The core sets this bit if there is a change in connector ID status.
-
Periodic TxFIFO Empty
Asserted if the Periodic Transmit FIFO is either half or completely
empty and there is space for at least one entry to be written in the
Periodic Request Queue. The half or completely empty status is
determined by the Periodic TxFIFO Empty Level bit in the Core
AHB Configuration register.
Host Channels Interrupt
The core sets this bit to indicate that an interrupt is pending on
one of the channels of the core (in Host mode). The application
must read the Host All Channels Interrupt (HAINT) register to
determine the exact number of the channel on which the interrupt
occurred, and then read the corresponding Host Channel-n
Interrupt (HCINTn) register to determine the exact cause of the
interrupt. The application must clear the appropriate status bit in
the HCINTn register to clear this bit.
Host Port Interrupt
The core sets this bit to indicate a change in port status of one of
the OTG core ports in Host mode. The application must read the
Host Port Control and Status (HPRT) register to determine the
exact event that caused this interrupt. The application must clear
the appropriate status bit in the Host Port Control and Status
register to clear this bit.
-
Description
S5PC100 USER'S MANUAL (REV1.0)
R/W
R_SS
_WC
R_SS
_WC
R_SS
_WC
R_SS
_WC
R
R
R
Reset
Value
1'b0
1'b0
1'b0
1'b0
1'b0
1'b1
1'b0
1'b0
1'b0