Samsung S5PC100 User Manual page 433

S5PC100 USER'S MANUAL (REV1.0)
4.1 SMC BUS WIDTH & WAIT CONTRL REGISTER (SMC_BW, RW, ADDRESS=0XE700_0000)
Field Bit
Reserved [31:24]
ByteEnable5 [23]
WaitEnable5 [22]
AddrMode5 [21]
DataWidth5 [20]
ByteEnable4 [19]
WaitEnable4 [18]
AddrMode4 [17]
DataWidth4 [16]
ByteEnable3 [15]
WaitEnable3 [14]
Reserved
nWBE / nBE(for UB/LB) control for Memory Bank5
0 = Not using UB/LB (XrnWBE[1:0] is dedicated nWBE[1:0])
1 = Using UB/LB (XrnWBE[1:0] is dedicated nBE[1:0]
Enables Wait for Memory Bank5
0 = Disables WAIT
1 = Enables WAIT
Select SMC ADDR Base for Memory Bank5
0 = SMC_ADDR is Half-word base address.
(SRAM_ADDR[20:0] ← HADDR[21:1])
1 = SMC_ADDR is byte base address
(SMC_ADDR[20:0] ← HADDR[20:0])
Note: If DataWidth0 is "0", SMC_ADDR is byte base address.
(Ignored this bit.)
Data bus width control for Memory Bank5
0 = 8-bit
1 = 16-bit
nWBE / nBE(for UB/LB) control for Memory Bank4
0 = Not using UB/LB (XrnWBE[1:0] is dedicated nWBE[1:0])
1 = Using UB/LB (XrnWBE[1:0] is dedicated nBE[1:0]
Enables Wait for Memory Bank4
0 = Disables WAIT
1 = Enables WAIT
Select SMC ADDR Base for Memory Bank4
0 = SMC_ADDR is Half-word base address.
(SRAM_ADDR[20:0] ← HADDR[21:1])
1 = SMC_ADDR is byte base address
(SMC_ADDR[20:0] ← HADDR[20:0])
Note: If DataWidth0 is "0", SMC_ADDR is byte base address.
(Ignored this bit.)
Data bus width control for Memory Bank4
0 = 8-bit
1 = 16-bit
nWBE / nBE(for UB/LB) control for Memory Bank3
0 = Not using UB/LB (XrnWBE[1:0] is dedicated nWBE[1:0])
1 = Using UB/LB (XrnWBE[1:0] is dedicated nBE[1:0]
Wait enable control for Memory Bank3
0 = Disables WAIT
1 = Enables WAIT
Description
STATIC MEMORY CONTROLLER
Reset Value
0
0
0
0
0
0
0
0
0
0
0
5.2-7