Samsung S5PC100 User Manual page 675

SPI CONTROLLER
4.2.5 SPI Interrupt Enable Register
•
SPI_INT_EN0, R/W, Address = 0xEC30_0010
•
SPI_INT_EN1, R/W, Address = 0xEC40_0010
•
SPI_INT_EN2, R/W, Address = 0xEC50_0010
SPI_INT_ENn
INT_EN_TRAILING
INT_EN_RX_OVERRUN
INT_EN_RX_UNDERRUN
INT_EN_TX_OVERRUN
INT_EN_TX_UNDERRUN
INT_EN_RX_FIFO_RDY
INT_EN_TX_FIFO_RDY
8.3-10
Bit
Interrupt Enable for trailing count to be 0
[6]
0 = Disable
Interrupt Enable for RxOverrun
[5]
0 = Disable
Interrupt Enable for RxUnderrun
[4]
0 = Disable
Interrupt Enable for TxOverrun
[3]
0 = Disable
Interrupt Enable for TxUnderrun. In slave mode, this bit
[2] must be clear first after turning on slave TX path.
0 = Disable
Interrupt Enable for RxFifoRdy (INT mode)
[1]
0 = Disable
Interrupt Enable for TxFifoRdy (INT mode)
[0]
0 = Disable
S5PC100 USER'S MANUAL (REV1.0)
Description
1 = Enable
1 = Enable
1 = Enable
1 = Enable
1 = Enable
1 = Enable
1 =Enable
Reset Value
0
0
0
0
0
0
0