Samsung S5PC100 User Manual page 287

S5PC100 USER'S MANUAL (REV1.0)
3.2.1 HPM Delay
Critical path delay of ARM Core in S5PC100X is about 1.70ns in the worst condition. Delay of NOR2X1 cell is
about 0.04609ns. One delay tap has four NOR2X1 cells and each delay tap gives 0.184ns delay. Delay tap
structure is as shown in Figure 2.5-6.
HPM has a predelay module that includes 32 delay tap-like delay elements and a delayline module that includes
32 delay taps. To correlate with ARM core, 14-th tap should be selected with setting predelay_sel[2:0] of HPM
3'b000 when HPM clock ratio is equal to 1.
3.2.2 Calibration Code for Closed-loop
In closed-loop mode, Calibration codes are used to control voltage level, while voltage values in open-loop mode.
Calibration code stands for critical path delay of ARM core. In S5PC100X, 14-th tap output of HPM has the nearly
same delay to the critical path of ARM core (when HPM clock ratio is equal to 1), which can be encoded to the
delay code 5'hE.
3.3 INITIALIZATION SEQUENCE
1). Initialize the index map & all other IEM & APC mapping values.
2) If IEM will use 'overdrive' level, then programs 'Max performance mapping index value' in IECDPCCR register
with proper values ( smaller than 3'b111)
3) Enables voltage scaling feature in the APC by setting 'APC_VDD_UD' bit in APC_CONTROL register as "1"
4) If IEM will use closed loop mode, then programs 'APC_HPM_EN' bit & 'APC_LOOP_MODE' bit in
APC_CONTROL register as "1"
5) Start IEM HW by setting 'iem_enable' bit in IEM_CONTROL register in power management unit as "1"
6) Start IEM control by setting "iec_enable" bit in IECDPCCR register as "1"
7) Now, the system is under the IEM control.
Figure 2.5-6 HPM Delay Tap Structure in S5PC100X
INTELLIGENT ENERGY MANAGEMENT
2.5-15