Samsung S5PC100 User Manual page 805

S5PC100 USER'S MANUAL (REV1.0)
3.1.3 USB Block Diagram
AHB Slave interface
AHB
Master/Slave
Interface
AHB
Master/Slave
Interface
The S5PC100x USB system shown in Figure 8.9-3 is configured as following:
1. USB 1.1 Host 1 Port & USB 2.0 OTG 1 Port
2. USB 1.1 Host 2 Ports
Note: To enable Serial Interface 1 and use 2 ports of Host 1.1, set the OPHYCLK.serial_mode register bit to 1.
PHY Clock
USB 2.0
OTG LINK
UTMI Interface
Serial Interface 1
USB 1.1
Host
48Mhz Clock
Serial Interface 2
Figure 8.9-3 System Level Block Diagram
(30 Mhz)
USB 2.0
PHY CONTROL
PHY Clock
(30 Mhz)
USB 2.0
OTG PHY
USB 1.1
Transceiver
USB HOST CONTROLLER
PHY Control Signal
(clk_sel, etc )
Crystal or Oscillator
XusbXTI
XusbXTO
XusbDP
XusbDM
USB Host
or Device
XuhDP
XuhDN
External
8.9-5