Samsung S5PC100 User Manual page 308

INTELLIGENT ENERGY MANAGEMENT
5.3.24 Voltage Information Registers
APC1 has two types of voltage information registers. Ones are for closed-loop control, and the others are for
open-loop control. Registers for closed-loop control give delay information, while registers for open-loop control
give direct voltage information. There is a register containing the retention voltage level for the performance level
zero.
Calibration Code Registers (APC_PL1_CALCODE, R/W, Address = 0xE100_0080)
Calibration Code Registers (APC_PL2_CALCODE, R/W, Address = 0xE100_0084)
Calibration Code Registers (APC_PL3_CALCODE, R/W, Address = 0xE100_0088)
Calibration Code Registers (APC_PL4_CALCODE, R/W, Address = 0xE100_008C)
Calibration Code Registers (APC_PL5_CALCODE, R/W, Address = 0xE100_0090)
Calibration Code Registers (APC_PL6_CALCODE, R/W, Address = 0xE100_0094)
Calibration Code Registers (APC_PL7_CALCODE, R/W, Address = 0xE100_0098)
Calibration Code Registers (APC_PL8_CALCODE, R/W, Address = 0xE100_009C)
The Calibration Code Registers are eight, 5-bit registers. Their names are APC_PL1_CALCODE ~
APC_PL8_CALCODE. They give delay information target for closed-loop operation.
APC_PL*_CALCODE
Reserved
Reference Calibrated Code 1
Open-loop VDD Core Registers (APC_PL1_COREVDD, R/W, Address = 0xE100_00A0)
Open-loop VDD Core Registers (APC_PL2_COREVDD, R/W, Address = 0xE100_00A4)
Open-loop VDD Core Registers (APC_PL3_COREVDD, R/W, Address = 0xE100_00A8)
Open-loop VDD Core Registers (APC_PL4_COREVDD, R/W, Address = 0xE100_00AC)
Open-loop VDD Core Registers (APC_PL5_COREVDD, R/W, Address = 0xE100_00B0)
Open-loop VDD Core Registers (APC_PL6_COREVDD, R/W, Address = 0xE100_00B4)
Open-loop VDD Core Registers (APC_PL7_COREVDD, R/W, Address = 0xE100_00B8)
Open-loop VDD Core Registers (APC_PL8_COREVDD, R/W, Address = 0xE100_00BC)
The Open-loop VDD Core Registers are eight, 7-bit registers. Their names are APC_PL1_COREVDD ~
APC_PL8_COREVDD. They give direct voltage information for open-loop operation.
APC_PL*_COREVDD
Reserved
OL_VDD1
2.5-36
Bits
[7:5] Read undefined. Write as zero.
[4:0] The RCC for performance level *
Bits
[7] Read undefined. Write as zero.
[6:0] The voltage value for the performance level * in the
open-loop mode.
S5PC100 USER'S MANUAL (REV1.0)
Description
Description
Reset Value
X
0x1F
Reset Value
X
0x7F