Samsung S5PC100 User Manual page 437

S5PC100 USER'S MANUAL (REV1.0)
Field
Tcah
Tacp
Reserved
Reserved
Bit
Address holding time after nGCSn
0000 = 0 clock
0010 = 2 clocks
[11:8] .............
1100 = 12 clocks
1110 = 14 clocks
Note: More 1~2 cycles according to bus i/f status
Succesive access cycle
0000 = 0 clock
0010 = 2 clocks
[7:4]
.............
1100 = 12 clocks
1110 = 14 clocks
[3:2] Reserved
[1:0] Should be zero.
STATIC MEMORY CONTROLLER
Description
0001 = 1 clocks
0011 = 3 clocks
1101 = 13 clocks
1111 = 15 clocks
0001 = 1 clocks
0011 = 3 clocks
1101 = 13 clocks
1111 = 15 clocks
Reset Value
0000
0000
00
5.2-11