Samsung S5PC100 User Manual page 640

UART
UART FIFO Control Register
•
UFCON0, R/W, Address = 0xEC00_0008
•
UFCON1, R/W, Address = 0xEC00_0408
•
UFCON2, R/W, Address = 0xEC00_0808
•
UFCON3, R/W, Address = 0xEC00_0C08
There are four UART FIFO control registers namely UFCON0, UFCON1, UFCON2 and UFCON3 in the UART
block.
UFCONn Bit
Tx FIFO Trigger [7:6]
Level
Rx FIFO Trigger [5:4]
Level
Reserved
Tx FIFO Reset
Rx FIFO Reset
FIFO Enable
NOTE: For using RX DMA in FIFO mode, Rx FIFO trigger level must be same value as DMA burst size.
When using DMA single operation, RX FIFO trigger level must be set to 1-byte.
8.1-16
Determines the trigger level of transmit FIFO.
00 = Empty
10 = 32-byte
Determines the trigger level of receive FIFO.
00 = 1-byte
10 = 16-byte
[3]
[2] Auto-cleared after resetting FIFO
0 = Normal
[1] Auto-cleared after resetting FIFO
0 = Normal
[0] 0 = Disable
S5PC100 USER'S MANUAL (REV1.0)
Description
01 = 16-byte
11 = 48-byte
01 = 8-byte
11 = 32-byte
1= Tx FIFO reset
1= Rx FIFO reset
1 = Enable
Reset Value
00
00
0
0
0
0