Samsung S5PC100 User Manual page 346

ASYNC BRIDGE
1.3 OPERATION OF ASYNCHRONOUS BRIDGE
1.3.1 Normal Operation
Almost all functionality is provided by the five logically identical FIFOs and this section describes their operation.
Figure 3.4-3 shows the internal structure of a FIFO.
Figure 3.4-3 Internal Structure of a Four-Place Asynchronous FIFO
The asynchronous FIFOs are implemented as an array of data storage elements in parallel. The write enables
and read multiplexing are controlled by separate circular counters that operate in each clock domain. The data
storage elements provide the mechanism for data to cross the timing boundary.
The read counter is made available to the write process and the write counter is made available to the read
process. This determines when the FIFO is either:
•
Full, and cannot be written to
•
Empty, and cannot be read from.
3.4-4
S5PC100 USER'S MANUAL (REV1.0)