Samsung S5PC100 User Manual page 828

USB HOST CONTROLLER
UHCFMI Bit
FIT [31]
FSMPS [30:16]
Reserved [15:14]
FI [13:0]
5.2.15 USB HcFmRemaining Register (UHCFMRM, R, Address = 0xED40_0038)
The UHC Frame Remaining (UHCFMRM) register is a 14-bit down counter showing the bit-time remaining in the
current frame.
8.9-28
Table 8.9-14 UHCFMI Bit Definitions
FrameIntervalToggle
HCD toggles this bit whenever it loads a new value to
FrameInterval
FSLargestDataPacket
This field specifies a value that is loaded into the Largest
Data Packet counter at the beginning of each frame. The
counter value represents the largest amount of data in bits
that is sent or received by the UHC in a single transaction at
any given time without causing scheduling overrun. The field
value is calculated by the HCD.
Reserved
FrameInterval
This specifies the interval between two consecutive SOFs in
bit-times. The nominal value is set at 11,999. HCD must
store the current value of this field before resetting UHC (by
setting the HostControllerReset field of HcCommandStatus,
Refer to Section 20.8.3) as this causes the UHC to reset this
field to its nominal value. The HCD chooses to restore the
stored value upon the completion of the reset sequence.
Description
S5PC100 USER'S MANUAL (REV1.0)
R/W Reset Value
R/W
R/W
-
R/W