Samsung S5PC100 User Manual page 656

2
I C-BUS INTERFACE
SDA
MSB
1
SCL
S
1.4 ACK SIGNAL TRANSMISSION
To complete a one-byte transfer operation, the receiver sends an ACK bit to the transmitter. The ACK pulse
occurs at the ninth clock of the SCL line. Eight clocks are required for the one-byte data transfer. The master
generates the clock pulse required to transmit the ACK bit.
The transmitter releases the SDA line by making the SDA line High if the ACK clock pulse is received. The
receiver drives the SDA line Low during the ACK clock pulse so that the SDA keeps Low during the High period of
the ninth SCL pulse.
The software (I2CSTAT) enables or disables ACK bit transmit function. However, the ACK pulse on the ninth
clock of SCL is required to complete the one-byte data transfer operation.
Data Output by
Transmitter
Data Output by
Receiver
SCL from
Master
Condition
8.2-4
Acknowledgement
Signal from Receiver
2 7 8
Byte Complete, Interrupt
within Receiver
Figure 8.2-4 Data Transfer on the I
1
S
Start
Figure 8.2-5 Acknowledge on the I
9 1 2
ACK
Clock Line Held Low by
receiver and/or transmitter
2
C-Bus
2
2
C-Bus
S5PC100 USER'S MANUAL (REV1.0)
Acknowledgement
Signal from Receiver
9
Clock to Output
7 8 9
Clock Pulse for Acknowledgment