Samsung S5PC100 User Manual page 1011

SD/MMC CONTROLLER
CONTROL2 Bit
ENBUSYCH [11]
KTXSTART
DFCNT [10:9]
ENCLKOUTH [8]
OLD
RWAITMOD [7]
E
DISBUFRD [6]
SELBASE [5:4]
CLK
SDINPSIGPC [3]
- Reserved [2]
ENCLKOUT [1]
MSKCON
HWINITFIN [0]
NOTES:
1. Ensure to set SDCLK Hold Enable (EnSCHold) if the card does not support Read Wait to guarantee for
Receive data not overwritten to the internal FIFO memory.
2. CMD_wo_DAT issue is prohibited during READ transfer if SDCLK Hold Enable is set.
8.12-76
CE-ATA I/F mode
Busy state check before Tx Data start state
0 = Disable, 1 = Enable
Debounce Filter Count
Debounce Filter Count setting register for Card Detect signal input
(SDCD#)
00 = No use debounce filter, 01 = 4 iSDCLK,
10 = 16 iSDCLK,
SDCLK Hold Enable
Enter and exit of the SDCLK Hold state is done by Host Controller.
0 = Disable, 1 = Enable
Read Wait Release Control
0 = Read Wait state is released by the Host Controller (Auto)
1 = Read Wait state is released by the Host Driver (Manual)
Buffer Read Disable
0 = Normal mode, user can read buffer(FIFO) data using 0x20 register
1 = User cannot read buffer(FIFO) data using 0x20 register. In this
case, the buffer memory is read through memory area (Debug
purpose).
Base Clock Source Select
00 or 01 = HCLK, 10 = SCLK_MMC0, SCLK_MMC1, SCLK_MMC2
(from CLKCON), 11 = SCLK_MMC0_48, SCLK_MMC1_48,
SCLK_MMC2_48, (XTI or XEXTCLK)
SD Input Signal Power Control Support
If set this field enables input CMD and DAT referencing SD Bus Power
bit in the "PWRCON register".
'0' = No Sync, no switch input enable signal (Command, Data)
'1' = Sync, control input enable signal (Command, Data)
Reserved
SDCLK output clock masking when Card Insert cleared
If this field is High, it is used not to stop SDCLK if No Card state.
'0' = Disable, '1' = Enable
SD Host Controller Hardware Initialization Finish
0 = Not Finish, 1 = Finish
Description
11 = 64 iSDCLK
S5PC100 USER'S MANUAL (REV1.0)
Reset Value
0
0
0
0
0
00
0
0
0
0