Samsung S5PC100 User Manual page 970

S5PC100 USER'S MANUAL (REV1.0)
Response Bit Definition for Each Response Type.
Kind of Response
R1, R1b (normal response)
R1b (Auto CMD12 response)
R2 (CID, CSD register)
R3 (OCR register)
R4 (OCR register)
R5,R5b
R6 (Published RCA response)
The Response Field indicates bit positions of "Responses" defined in the PHYSICAL LAYER SPECIFICATION
Version 1.01. The Table (above) shows that most responses with a length of 48 (R[47:0]) have 32 bits of the
response data (R[39:8]) stored in the Response register at REP[31:0]. Responses of type R1b (Auto CMD12
responses) have response data bits R[39:8] stored in the Response register at REP[127:96]. Responses with
length 136 (R[135:0]) have 120 bits of the response data (R[127:8]) stored in the Response register at
REP[119:0].
To be able to read the response status efficiently, the Host Controller only stores part of the response data in the
Response register. This enables the Host Driver to efficiently read 32 bits of response data in one read cycle on a
32-bit bus system. Parts of the response, the Index field and the CRC, are checked by the Host Controller (as
specified by the Command Index Check Enable and the Command CRC Check Enable bits in the Command
register) and generate an error interrupt if an error is detected. The bit range for the CRC check depends on the
response length. If the response length is 48, the Host Controller checks R[47:1], and if the response length is
136 the Host Controller checks R[119:1].
Since the Host Controller may have a multiple block data DAT line transfer executing concurrently with a
CMD_wo_DAT command, the Host Controller stores the Auto CMD12 response in the upper bits (REP[127:96]) of
the Response register. The CMD_wo_DAT response is stored in REP[31:0]. This allows the Host Controller to
avoid overwriting the Auto CMD12 response with the CMD_wo_DAT and vice versa.
If the Host Controller modifies part of the Response register, as shown in the Table above, it shall preserve the
unmodified bits.
9.8 BUFFER DATA PORT REGISTER
Buffer Data Register
•
BDATA0, R/W, Address = 0xED80_0020
•
BDATA1, R/W, Address = 0xED90_0020
•
BDATA2, R/W, Address = 0xEDA0_0020
32-bit data port register to access internal buffer.
BDATA Bit
BUFDAT [31:0] Buffer Data
The Host Controller buffer is accessed through this 32-bit single port SRAM
memory. Write and Read memories are separated.
NOTE: Detailed documents are to be copied from SD Host Standard Specification.
Meaning of Response
Card Status
Card Status for Auto CMD12
CID or CSD reg. incl.
OCR register for memory
OCR register for I/O etc
SDIO response
New published RCA[31:16] etc
Description
SD/MMC CONTROLLER
Response Field Response Register
R [39:8]
R [39:8]
R [127:8]
R [39:8]
R [39:8]
R [39:8]
R [39:8]
REP [31:0]
REP [127:96]
REP [119:0]
REP [31:0]
REP [31:0]
REP [31:0]
REP [31:0]
Reset Value
Not fixed
8.12-35