Samsung S5PC100 User Manual page 491

NAND FLASH CONTROLLER
7.16 SPARE AREA ECC STATUS REGISTER (NFSECC, R, ADDRESS = 0XE720_003C)
NFSECC
SECC1_1
SECC1_0
SECC0_1
SECC0_0
NOTE: The NAND flash controller generates NFSECC if read or write spare area data while the
SpareECCLock(NFCONT[6]) bit is '0'(Unlock).
7.17 MLC 4-BIT ECC ERROR PATTEN REGISER (NFMLCBITPT, R, ADDRESS = 0XE720_0040)
NFMLCBITPT
th
4 Error bit pattern
rd
3 Error bit pattern
nd
2 Error bit pattern
st
1 Error bit pattern
5.4-26
Bit
[31:24] Spare area ECC1 Status for I/O[15:8]
[23:16] Spare area ECC0 Status for I/O[15:8]
[15:8] Spare area ECC1 Status for I/O[7:0]
[7:0] Spare area ECC0 Status for I/O[7:0]
Bit
th
[31:24]
4 Error bit pattern
rd
[23:16]
3 Error bit pattern
nd
[15:8]
2 Error bit pattern
st
[7:0]
1 Error bit pattern
S5PC100 USER'S MANUAL (REV1.0)
Description
Description
Reset Value
0x03
0xFF
0x03
0xFF
Reset Value
0x00
0x00
0x00
0x00