Samsung S5PC100 User Manual page 288

INTELLIGENT ENERGY MANAGEMENT
3.4 PWI (POWER WISE INTERFACE)
The PWI master drives the PWI clock line. Although a pull-down resistor is connected between the SCLK and
GND-voltage on the slave, the PWI master drives the clock signal actively high and low.
The SCLK frequency range is 0 MHz ~ 15 MHz. The clock runs only when data is being transferred. Otherwise
the SCLK signal line is at logic low voltage. Minimum pulse width of the clock signal is 26ns.
The PWI data-line is bi-directional. Data is written on the falling edge of the SCLK and read on the rising edge of
the SCLK.
4 I/O DESCRIPTION
Function Signal
IEM_SCLK
IEM_SPWI
NOTE: Type field indicates whether pads are dedicated to the signal or pads are connected to the multiplexed signals.
2.5-16
I/O
Bidirectional
Bidirectional
Description
PWI clock
PWI serial data
S5PC100 USER'S MANUAL (REV1.0)
Pad
XiemSCLK dedicated
XiemSPWI dedicated
type