Samsung S5PC100 User Manual page 167

S5PC100 USER'S MANUAL (REV1.0)
7.6 FIMD AND FIMC
CLK54M
HPLLout
MPLLout
EPLLout
CLK54M
HPLLout
MPLLout
EPLLout
CLK54M
HPLLout
MPLLout
EPLLout
CLK54M
HPLLout
MPLLout
EPLLout
FIMD (LCD controller) and three FIMCs (Camera interface) have many clock sources. Figure 2.3-109 shows
overall clock path and registers to set. SCLK_FIMCn is the local interface clock between FIMCn and FIMD.
SCLK_LCD
SCLK_FIMC0
FIMC0
DCLK
HCLKD1
SCLK_FIMC1
FIMC1
DCLK
HCLKD1
SCLK_FIMC2
FIMC2
DCLK
HCLKD1
FIMC DCLK is not used in DMA write mode
Figure 2.3-9 FIMD and FIMC clock
CLOCK CONTROLLER
W0_LCLK
FIMD
W1_LCLK
W2_LCLK
HCLKD1
2.3-17