Samsung S5PC100 User Manual page 815

S5PC100 USER'S MANUAL (REV1.0)
UHCCONSTAT Bit
BLF
CLF
HCR
[2] BulkListFilled
This bit indicates whether there are any TDs on the bulk
list. It is set by the host controller driver whenever it
adds a TD to an ED in the bulk list. If UHC begins to
process the head of the bulk list, it checks the
BulkListFilled bit (BLF). As long as BulkListFilled is 0,
UHC does not start processing the bulk list. If
BulkListFilled is 1, UHC starts processing the bulk list
and sets BLF to 0. If UHC finds a TD on the list, then
UHC sets BulkListFilled to 1, causing the bulk list
processing to continue. If no TD is found on the bulk list,
and if the host controller driver does not set
BulkListFilled, then BulkListFilled is still 0 if UHC
completes processing the bulk list, and bulk list
processing stops.
0 = Bulk list processing stops.
1 = HC starts processing the bulk list and sets BLF to 0.
[1] ControlListFilled
This bit indicates whether there are any TDs on the
control list. It is set by the host controller driver
whenever it adds a TD to an ED in the control list. If
UHC begins to process the head of the control list, it
checks the control list filled (CLF) bit. As long as CLF is
0, UHC does not start processing the Control list. If CF
is 1, UHC starts processing the control list and sets CLF
to 0. If UHC finds a TD on the list, then UHC sets CLF to
1 causing the control list processing to continue. If no
TD is found on the control list, and if the host controller
driver does not set CLF, then it is still 0, if UHC
completes processing the control list, and control list
processing stops.
0 = UHC does not start processing the control list.
1 = UHC starts processing the control list and sets
ControlListFilled to 0.
[0] HostControllerReset
The host controller driver sets this bit to initiate a
software reset of UHC. Regardless of the functional
state of the UHC, it moves to the USBSUSPEND state in
which most of the operational registers are reset. The
exceptions to that are stated in the OHCI Spec (for
example, the InterruptRouting field of the UHC Host
Control register). While this bit is set, no USB host bus
accesses are allowed (writes or reads of the OHCI
registers). This bit is cleared by the UHC upon the
completion of the reset operation (which is completed
within 10 μs.). This bit, if set, does not cause a reset to
the root hub and no subsequent reset signaling is
asserted to its downstream ports.
0 = Controller is not in reset.
1 = Reset the host controller.
Description
USB HOST CONTROLLER
R/W Reset Value
R/W
R/W
R/W
8.9-15