Samsung S5PC100 User Manual page 773

S5PC100 USER'S MANUAL (REV1.0)
3.2 DETAILED DECRIPTION
3.2.1 Status Register (DSIM_STATUS, R, Address = 0xECB0_0000)
This registers reads and checks status Internal & interface status.
FSM status, Line buffer status, current image line number, etc.
DSIM_STATUS
PllStable
Reserved
SwRstRls
Reserved
Direction
Reserved
TxReadyHsClk
UlpsClk
StopstateClk
UlpsDat[3:0]
StopstateDat[3:0]
Bit
[31] D-phy pll generates stable byteclk.
[30:21] Reserved
[20] Software reset status
0 = Reset state
1 = Release state
[19:17] Reserved
[16] Data direction indicator
0 = Forward direction
1 = Backward direction
[15:11] Reserved
[10] HS clock ready at Clock lane
0 = Not ready for transmitting HS data at clock lane.
1 = Ready for transmitting HS data at clock lane.
[9] ULPS indicator at clock lane
0 = No ULPS in clock lane
1 = ULSP in clock lane
[8] Stop state indicator at clock lane
0 = No Stop state in clock lane
1 = Stop state in clock lane
[7:4] ULPS indicator at data lanes
UlpsDat[0] : Data lane 0
UlpsDat[1] : Data lane 1
UlpsDat[2] : Data lane 2
0 = No ULPS in each data lane.
1 = ULPS in each data lane.
[3:0] Stop state indicator at data lane
StopstateDat[0] : Data lane 0
StopstateDat[1] : Data lane 1
StopstateDat[2] : Data lane 2
0 = No Stop state in each data lane
1 = Stop state in each data lane
Description
MIPI DSIM
R/W Reset Value
R 0
- 0
R 0
- 0
R 1
- 0
R 0
R 1
R 0
R F
R 0
8.7-17