Samsung S5PC100 User Manual page 192

CLOCK CONTROLLER
10.5.7 Control HCLKD1 / PCLKD1 Clock Gating 2 (Multimedia2) (CLK_GATE_D1_2, R/W, Address =
0xE010_0528)
D1 domain Multimedia2 system clock gating
CLK_GATE_D1_2
Reserved
CLK_MFC
CLK_HDMI
CLK_MIXER
CLK_VP
CLK_TV
10.5.8 Control HCLKD1 / PCLKD1 Clock Gating 1 (System) (CLK_GATE_D1_3, R/W, Address =
0xE010_052C)
D1 domain system control clock gating
CLK_GATE_D1_3
Reserved
CLK_RTC
CLK_WDT
CLK_SYSTIMER
CLK_PWM
Reserved
Reserved
CLK_IEC
CLK_APC
CLK_GPIO
CLK_CHIPID
2.3-42
Bit
[31 : 5] Reserved
[4] Gating HCLK & PCLK for MFC (0: Mask, 1: Pass)
[3] Gating HCLK for HDMI (0: Mask, 1: Pass)
[2] Gating HCLK for MIXER (0: Mask, 1: Pass)
[1] Gating HCLK for VP (0: Mask, 1: Pass)
[0] Gating HCLK for TV encoder (0: Mask, 1: Pass)
Bit
[31:10] Reserved
[9] Gating PCLK for RTC (0: Mask, 1: Pass)
[8] Gating PCLK for watch dog timer (0: Mask, 1: Pass)
[7] Gating PCLK for system timer (0: Mask, 1: Pass)
[6] Gating PCLK for PWM (0: Mask, 1: Pass)
[5] Do not change this value
[4] Do not change this value
[3] Gating PCLK for IEM_IEC (0: Mask, 1: Pass)
[2] Gating PCLK for IEM_APC (0: Mask, 1: Pass)
[1] Gating PCLK for GPIO (0: Mask, 1: Pass)
[0] Gating PCLK for chip ID (0: Mask, 1: Pass)
S5PC100 USER'S MANUAL (REV1.0)
Description
Description
Reset Value
0
1
1
1
1
1
Reset Value
0
1
1
1
1
1
1
1
1
1
1