Samsung S5PC100 User Manual page 571

S5PC100 USER'S MANUAL (REV1.0)
3.2.11 Configuration Register2 for DMA_MEM (CR2, R, Address=0xE810_0E08)
CR2
boot_addr
3.2.12 Configuration Register3 for DMA_MEM (CR3, R, Address=0xE810_0E0C)
CR3
INS
3.2.13 Configuration Register4 for DMA_MEM (CR4, R, Address=0xE810_0E10)
CR4
PNS
Bit
Provides the value of boot_addr[31:0] when the DMAC exited
from reset
[31:0]
32'b0
Bit
Provides the security state of the interrupt outputs
Bit [N] = 1 Assigns irq[N] to the Non-secure state
[31:0]
32'hffff_ffff
Bit
Provides the security state of the peripheral request interfaces:
Bit [N] = 1 Assigns peripheral request interface N to the Non-
[31:0]
secure state.
b11
Description
Description
Description
DMA CONTROLLER
Reset Value
0
Reset Value
0xFFFF_FFFF
Reset Value
0x3
6.1-23