Samsung S5PC100 User Manual page 569

S5PC100 USER'S MANUAL (REV1.0)
3.2.7 Configuration Register4 for DMA_PERI(0,1) (CR4, R)
•
CR4 for DMA_PERI0, R, Address = 0xE900_0E10
•
CR4 for DMA_PERI1, R, Address = 0xE920_0E10
CR4
PNS
3.2.8 Configuration Register DN for DMA_PERI(0,1) (CRdn, R)
•
CRDn for DMA_PERI0, R, Address = 0xE900_0E14
•
CRDn for DMA_PERI1, R, Address = 0xE920_0E14
CRDn
data_buffer_dep
rd_q_dep
rd_cap
wr_q_dep
wr_cap
data_width
Bit
Provides the security state of the peripheral request interfaces:
Bit [N] = 1 Assigns peripheral request interface N to the Non-
[31:0]
secure state.
32'hffff_ffff
Bit
The number of lines that the data buffer contains
[29:20]
b000000111 = 8 lines
The depth of the read queue
[19:16]
b0111 = 8 lines
Read issuing capability that programs the number of
outstanding read transactions
[14:12]
b011 = 4
The depth of the write queue
[11:8]
b0111 =8 lines
Write issuing capability that programs the number of
outstanding write transactions
[6:4]
b011 = 4
The data bus width of the AXI interface
[2:0]
b010 = 32-bit
Description
Description
DMA CONTROLLER
Reset Value
0xFFFF_FFFF
Reset Value
0x7
0x7
0x3
0x7
0x3
0x2
6.1-21