Samsung S5PC100 User Manual page 252

S5PC100 USER'S MANUAL (REV1.0)
1. Top Memory On bit must be applied with Top domain On configuration.
Top memory includes all SRAM inside IP module of Top domain.
If TOP_MEMORY_ON = 0, then you should determine power mode (retention or off) of each TOP memory by
setting STOP_MEM_CFG register before entering STOP/DEEP-STOP mode.)
2. ARM_L2CACHE_RET field is related ARM_LOGIC_ON as follows.)
ARM_L2CACHE_RET = 1'b0
ARM_L2CACHE_RET = 1'b1
3. If ARM_LOGIC_ON[17] = 1'b1, it is called STOP mode, and if ARM_LOGIC_ON[17] = 1'b0, it is called DEEP-
STOP mode. The available configurations of other bits of STOP_CFG register in each mode are shown below:
Note: [n]-bit offset of corresponding field in STOP_CFG register, TL-Top domain, TM-Top memory, AL-ARM
Logic, AM-ARM L2Cache, O-available configuration, X-unavailable configuration, ()-the constraint or reason
why that configuration is not supported
(1) STOP_mode : ARM_LOGIC_ON[17] = 1'b1
TL[8] TM[31]
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
ARM_LOGIC_ON = 1'b0
ARM L2CACHE OFF
ARM L2CACHE RETENTION
AL[17]
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
AM[29]
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Power Management
ARM_LOGIC_ON = 1'b1
ARM L2CACHE ON
N.A
Result
X (TL, AL should be 1)
X (TL, AL should be 1)
X (TL, AL should be 1)
X (TL, AL should be 1)
X (TL, AL should be 1)
X (TL, AL should be 1)
X (TL, AL should be 1)
X (TL, AL should be 1)
X (TL, AL should be 1)
X (TL, AL should be 1)
O
X (AL=1 and AM=1)
X (TL,AL should be 1)
X (TL,AL should be 1)
O
X (AL=1 and AM=1)
2.4-53