Samsung S5PC100 User Manual page 992

S5PC100 USER'S MANUAL (REV1.0)
ERRINTSTS
STACMDIDXERR
STACMDEBITERR
STACMDCRCERR
STACMDTOUTERR
Bit
Occurs if it detects one of following timeout conditions.
(1) Busy timeout for R1b, R5b type
(2) Busy timeout after Write CRC status
(3) Write CRC Status timeout
(4) Read Data timeout.
'1' = Timeout
'0' = No Error
[3] Command Index Error
Occurs if a Command Index error occurs in the command
response.
'1' = Error
'0' = No Error
[2] Command End Bit Error
Occurs if it detects that the end bit of a command response is 0.
'1' = End bit Error generated
'0' = No Error
[1] Command CRC Error
Command CRC Error is generated in two cases.
(1) If a response is returned and the Command Timeout Error is
set to 0 (indicating no timeout), this bit is set to 1 if it detects a
CRC error in the command response.
(2) The Host Controller detects a CMD line conflict by
monitoring the CMD line if a command is issued. If the Host
Controller drives the CMD line to 1 level, but detects 0 levels on
the CMD line at the next SDCLK edge, then the Host Controller
aborts the command (Stop driving CMD line) and set this bit to
1. The Command Timeout Error also set to 1 to distinguish CMD
line conflict.
'1' = Generates CRC Error
'0' = No Error
[0] Command Timeout Error
Occurs if no response is returned within 64 SDCLK cycles from
the end bit of the command. If the Host Controller detects a
CMD line conflict, in which case Command CRC Error also set
as shown in Table
cycles because the Host Controller aborts command.
'1' = Timeout
'0' = No Error
Description
33, this bit sets without waiting for 64 SDCLK
SD/MMC CONTROLLER
Reset Value
0
0
0
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