Samsung S5PC100 User Manual page 199

S5PC100 USER'S MANUAL (REV1.0)
10.6.10 MIPI D-PHY Control Register1 (MIPI_PHY_CON1, R/W, Address = 0xE020_0414)
MIPI_PHY_CON1
PLL_BYPASS_SEL
Reserved
FORCE_SWAP_EN
Reserved
M_DPDN_SWAP
S_DPDN_SWAP
Reserved
10.6.11 HDMI PHY Control Register0 (HDMI_PHY_CON0, R/W, Address = 0xE020_0420)
HDMI_PHY_CON0
Reserved
Bit
Master PPI I/F signal.
If it is high, the clock signal from M_EXTSERCLK is
selected for serial clock for the Master lane instead of
[31]
Master PLL. When it is low (default), Master PLL output is
selected for serial clock.
This is used for MIPI DSI.
[30:28] Reserved
Force DP/DN swap enable
0: Do not use swap.
[27]
1: Enable swap feature according to M_DPDN_SWAP &
S_DPDN_SWAP.
[26] Do not change this value
This is to prevent crossing PCB trace lines of DP/DN if the
master lane is connected to a slave lane on PCB board. If it
[25] is set to HIGH, all the Master's DP/DN signals are
swapped.
This is used for MIPI DSI.
Slave PPI I/F signal.
This is to prevent crossing PCB trace lines of DP/DN if the
[24] slave lane is connected to a master lane on PCB board. If
set to HIGH, all the Slave's DP/DN signals are swapped.
This is used for MIPI CSI.
[23:0] Do not change this value
Bit
[31:0] Do not change this value
Description
Description
CLOCK CONTROLLER
Reset Value
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Reset Value
0x0
2.3-49