Samsung S5PC100 User Manual page 472

S5PC100 USER'S MANUAL (REV1.0)
5.3 1-BIT ECC MODULE FEATURES
Generation of 1-bit ECC is controlled by the ECC Lock (MainECCLock, SpareECCLock) bit of the Control register.
If ECCLock is Low, H/W ECC modules generate ECC codes.
1-bit ECC Register Configuration
Following tables shows the configuration of 1-bit ECC value read from spare area of external NAND Flash
memory. To compare ECC parity code generated by the H/W modules, the format of ECC read from memory is
important.
1) 8-bit NAND Flash Memory Interface
Register
th
NFMECCD0
4
NFMECCD1
Register
NFSECCD
4-bit/ 8-bit ECC decoding scheme is different from 1bit ECC.
Bit [31:24]
rd
ECC for I/O[7:0] 3
Bit [31:24]
Not used
NOTE
Bit [23:16]
nd
ECC for I/O[7:0] 2
Not used
Bit [23:16]
nd
2
NAND FLASH CONTROLLER
Bit [15:8]
st
ECC for I/O[7:0] 1
Bit [15:8]
st
ECC for I/O[7:0] 1
Bit [7:0]
ECC for I/O[7:0]
Bit [7:0]
ECC for I/O[7:0]
5.4-7