Samsung S5PC100 User Manual page 459

ONENAND CONTROLLER
4.23 INTERRUPT PIN ENABLE REGISTER (INT_PIN_ENABLE, R/W, ADDRESS = 0XE710_01A0)
INT_PIN_ENABLE
Reserved
INT
4.24 INTERRUPT MONITOR CYCLE COUNT REGISTER (INT_MON_CYC, R/W, ADDRESS = 0XE710_01B0)
INT_MON_CYC
Reserved
Int_Mon_Cyc_ Cnt
4.25 ACCESS CLOCK REGISTER (ACC_CLOCK, R/W, ADDRESS = 0XE710_01C0)
ACC_CLOCK
Reserved
Access_Clocks
4.26 ERROR BLOCK ADDRESS REGISTER (ERR_BLK_ADDR, R, ADDRESS = 0XE710_01E0)
ERR_PAGE_ADDR_1
Reserved
FBA_Fail
5.3-22
Bit
[31:1] Reserved
Interrupt Pin Enable. Enables interrupt information to be
transmitted to the host. An interrupt is only sent to the host if a
bit is set in the int_error_status register, the corresponding bit
[0]
is set in the INT_ERR_MASK register AND this bit is set.
0 = Does not report interrupts
1 = Send interrupt information to the host.
Bit
[31:12] Reserved
Sets the number of cycles in between checks of the
int_error_status register and the memory device's status
[11:0]
register. This register is used if the Flash configuration register
bit IOBE is clear.
Bit
[31:3] Reserved
Sets the number of cycles required to cover the access time of
the Flash memory device.
Follows the formula (35ns / ClkPeriod ) + 1
2X Clock
[2:0]
166MHz
134
100
60
Bit
[31:12] Reserved
After a program, load or erase error interrupt, this register
[11:0]
holds the block address of the failing operation. Read-Only.
S5PC100 USER'S MANUAL (REV1.0)
Description
Description
Description
Flash Clock Access_Clocks
83MHz 3
67 3
50 2
30 2
Description
Reset Value
0
Reset Value
0x01F4
Reset Value
0x3
Reset Value
0