Samsung S5PC100 User Manual page 887

USB2.0 HS OTG
8.2.21 Host Frame Interval Register (HFIR, R/W, Address = 0xED20_0404)
This register stores the frame interval information for the current speed to which the core has enumerated
HFNUM Bit
Reserved [31:16]
FrInt [15:0]
8.2.22 Host Frame Number/Frame Time Remaining Register (HFNUM, R, Address = 0xED20_0408)
This register indicates the current frame number. It also indicates the time remaining in the current frame.
HFNUM Bit
FrRem [31:16] Frame Time Remaining
FrNum [15:0]
8.10 -44
-
Frame Interval
The value that the application programs to this field specifies the
interval between two consecutive SOFs (FS) or micro- SOFs (HS)
or Keep-Alive tokens (HS). This field contains the number of PHY
clocks that constitute the required frame interval. The default
value set in this field for a FS operation if the PHY clock frequency
is 60 MHz. The application can write a value to this register only
after the Port Enable bit of the Host Port Control and Status
register (HPRT.PrtEnaPort) has been set. If no value is
programmed, the core calculates the value based on the PHY
clock specified in the FS/ LS PHY Clock Select field of the Host
Configuration register (HCFG.FSLSPclkSel). Do not change the
value of this field after the initial configuration.
• 125 μs * (PHY clock frequency for HS)
• 1 ms * (PHY clock frequency for FS/LS)
Indicates the amount of time remaining in the current microframe
(HS) or frame (FS/ LS), in terms of PHY clocks. This field
decrements on each PHY clock. If it reaches zero, this field is
reloaded with the value in the Frame Interval register and a new
SOF is transmitted on the USB.
Frame Number
This field increment if a new SOF is transmitted on the USB, and
is reset to 0 if it reaches 16'h3FFF.
Description
Description
S5PC100 USER'S MANUAL (REV1.0)
R/W
R/W
R/W Reset Value
R
R
Reset
Value
16'h0
16'h17D7
16'h0
16'h0