Samsung S5PC100 User Manual page 227

Power Management
6.9.2 Retention I/O, IO_RET_RELEASE, and SDMMC_IO_RET_RELEASE
In DEEP-IDLE mode (top domain off), DEEP-STOP mode (top domain off) and SLEEP mode, GPIO setting to
normal I/O is lost due to power off. (See Figure 2.4-4) Therefore, these setting should be saved before power to
top domain is off (nSCALL_BLK_TOP = 1'b0), and restored after wakeup from power down mode if necessary.
Before entry to DEEP-IDLE (top off), DEEP-STOP (top off), and SLEEP mode, I/O setting is switched from GPIO
normal mode configuration register (GP*CON) to GPIO power down mode configuration register (GP*PDNCON),
and after wakeup from power down mode, I/O setting is switched from GPIO power down mode configuration
register (GP*PDNCON) to GPIO normal mode configuration register (GP*CON).
Four retention signals such as RET_EN0, RET_EN1, RET_LPA, and RET_SDMMC) are asserted to keep their
setting after switch from GP*CON to GP*PDNCON before entry to above power down modes, and released for
I/Os to be used in Normal mode after switching from GP*PDNCON to GP*CON. (See Figure 2.4-4).
In Figure 2.4-4, XnRSTOUT is asserted during above power down modes, and released after wakeup from those
power down modes.
The mapping between these retention signals and normal I/O is shown in Table 2.4-11.
After wakeup from power down mode, RET_EN0 signal is released automatically by hardware to access to/from
memory. GPIO setting should be done before the other retention signals are released.
RET_EN1 and RET_LPA are released by setting IO_RET_RELEASE[31] in OTHERS register to 1'b1, and
RET_SDMMC are released by setting SDMMC_IO_RET_RELEASE[22] in OTHERS register to 1'b1
Retention
Control
Signal
RET_EN0 Hardware Logic
RET_EN1
Set IO_RET
_RELEASE[31] to 1'b1
RET_LPA
Set SDMMC_IO_RET
RET_SDMMC
_RELEASE[22] to 1'b1
1. The following I/Os have different behavior from above retention I/Os.
1) Digital I/O, Alive I/O, controlled by alive register : XEINT[31:0]
This I/O is controlled by alive register, and therefore its setting is kept during and after power down
mode.
2) Digital I/O, Alive I/O, controlled by off register : XNFMOD[1:0]
This I/O is controlled by off register, and therefore its setting should be written into corresponding
register after wakeup reset. Its state during power down mode is different according to top domain on/off.
- DEEP-IDLE (top on), STOP, DEEP-STOP (top on) : keep its value in Normal mode
- DEEP-IDLE (top off), DEEP-STOP (top off), SLEEP : input mode (no pull up/down)
3) Digital I/O, Alive I/O, dedicated : XOM[4:0], XPWRGTON, XnBATF, XnRESET, XXTI(XXTO),
2.4-28
Table 2.4-11 Retention control signals and Related Digital I/O
Released by
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Related Digital I/O
M0 ports (Xm0*), M1 ports (Xm1*), XnRSTOUT
XXTI27,XXTO27, JTAG (Xj*), UART (Xu*), SPI (Xspi*), I2S1
(Xi2s1*), PWM (XpwmTOUT), I2C (Xi2c*), Camera Interface
(Xci*), LCD (Xv*), XPKG_MODE[1:0], XCLKOUT, IEM (Xiem*),
MODEM_IF (Xmsm*), XDDR2SEL, MMC2 ports (Xmmc2*),
XNFMOD[5:2]
Xi2s0CDCLK, Xi2s0LRCK, Xi2s0SCLK, Xi2s0SDI,
Xi2s0SDO[2:0]
MMC0, 1 ports (Xmmc0*, Xmmc1*)
S5PC100 USER'S MANUAL (REV1.0)
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