Samsung S5PC100 User Manual page 818

USB HOST CONTROLLER
UHCINTSTAT Bit
UE [4]
RD [3]
SF [2]
WDH [1]
SO [0]
8.9-18
Description
UnrecoverableError
This bit is set if UHC detects a system error not related
to USB. UHC must not proceed with any processing or
signaling before the system error has been corrected.
System errors such as incorrect buffer addressing
offsets or condition codes (Refer to OHCI Revision 1.0a
specification.). The HCD clears this bit by either writing a
1 to it, or by resetting the UHC OHCI core by generating
a software reset (writing a 1 to the
UHCCOMSTAT[HCR] bit).
0 = No system error is detected.
1 = UHC detected a system error not related to USB.
ResumeDetected
This bit is set if UHC detects that a device on the USB is
asserting resume-signaling. It is the transition from no-
resume-signaling to resume-signaling that sets this bit.
This bit is not set if HCD sets the USBRESUME state.
0 = No device is asserting resume-signaling.
1 = A device on the USB is asserting resume-signaling.
StartofFrame
This bit is set by UHC start of each frame and after the
update of HccaFrameNumber. UHC also generates a
SOF token at the same time.
1 = A start of a frame or an update of
HccaFrameNumber has occurred
WritebackDoneHead
This bit is set immediately after the UHC has written to
the value of the UHCDHead to an external the memory
location referred to (by the OHCI spec) as
HccaDoneHead. Additional updates of the
HccaDoneHead do not occur until this bit has been
cleared. HCD must clear this bit only after it has
saved the content of HccaDoneHead.
1 = UHC has written HcDoneHead to HccaDoneHead.
SchedulingOverrun
This bit is set if the USB schedule for the current frame
overruns, and after the update of HccaFrameNumber. A
scheduling overrun also causes the
SchedulingOverrunCount of UHCCOMS to be
incremented To avoid this condition, take care to enable
the periodic lists as early in the frame as possible.
Processing of the periodic lists occurs with no TDs
scheduled. If a list is enabled at the end of the frame,
and the reading of the lists occurs beyond the frame
boundary the SO bit is set to 0b1 and the SOC counter
is incremented.
1 = The USB schedule for the current frame has overrun
or the update of HccaFrameNumber has occurred.
S5PC100 USER'S MANUAL (REV1.0)
R/W Reset Value
R/WC
R/WC
R/WC
R/WC
R/WC