Samsung S5PC100 User Manual page 732

MIPI HSI INTERFACE CONTROLLER
2 FEATURES
The MIPI HSI Rx/ Tx controller features:
The MIPI HSI interface is uni-direction interface.
MIPI HSI maximum bandwidth is 200Mbps. The MIPI HSI Tx controller use PCLK for data transmitting.
Tx Module:
•
Status Register
♦ FIFO status (fifo full, fifo empty, fifo write point, fifo read point)
♦ MIPI status (internal status: current status & next status)
•
Configuration Register
♦ Select Operation mode (Stream mode or Frame mode)
♦ Fixed channel ID mode
♦ Number of channel
♦ Generated Error clear
♦ TxHOLD state timer and enable
♦ TxIDLE state timer and enable
♦ TxREQ state timer and enable
•
Interrupt Source Register
♦ FIFO empty
♦ Break frame transfer done
♦ TxHOLD state timeout
♦ TxIDLE state timeout
♦ TxREQ state timeout
•
Interrupt Mask Register
•
Software Reset Register
•
Channel ID Register
•
Data Register
♦ Tx FIFO input
♦ Tx FIFO size (Flip-Flop FIFO, not memory)
− 32-bit width X 32 depth (128-Byte)
8.6-2
S5PC100 USER'S MANUAL (REV1.0)