Samsung S5PC100 User Manual page 185

S5PC100 USER'S MANUAL (REV1.0)
10.3 CLOCK DIVIDER CONTROL REGISTER
S5PC100 has several clock dividers to support various operating clock frequency. CLK_DIV0, CLK_DIV1,
CLK_DIV2, CLK_DIV3, CLK_DIV4, and CLK_DIV_5 controls clock divider ratio.
There are operating frequency limitations. The maximum operating frequency of DOUT
DOUT , HCLKD1, and PCLKD1 are 266MHz, 266MHz, 133MHz, 133MHz, and 66MHz respectively. These
D1_BUS
operating clock conditions must be met through CLK_DIVX configuration.
10.3.1 Set Clock Divider Ratio 0 (Main D0 domain) (CLK_DIV0, R/W, Address = 0xE010_0300)
Main D0 domain divider
CLK_DIV0
Reserved
SECSS_RATIO
Reserved
PCLKD0_RATIO
Reserved
DO_BUS_RATIO
RESERVED
ARM_RATIO
Reserved
APLL_RATIO
At least one of the ARM clock dividers (DIV
refer to "Section 7.1".
Bit
[31:19] Reserved
DIV clock divider ratio,
SECSS
HCLKD0_SECSS = DOUT
SECSS_RATIO + 1)
[18:16]
SECSS (Secure Sub-System) operating clock cannot exceed
83MHz.
[15] Reserved
DIV clock divider ratio,
PCLKD0
[14:12]
PCLKD0 = HCLKD0 / RATIO (RATIO = PCLKD0_RATIO + 1)
[11] Reserved
DIV clock divider ratio,
D0_BUS
[10:8]
HCLKD0 = DOUT
[7] RESERVED
DIV clock divider ratio,
ARM
[6:4]
ARMCLK = DOUT
[3:1] Reserved
DIV clock divider ratio,
APLL
[0]
DOUT = MOUT
APLL
APLL
Description
/ RATIO (RATIO =
D0_BUS
/ RATIO (RATIO = D0_BUS_RATIO + 1)
ARM
/ RATIO (RATIO = ARM_RATIO + 1)
APLL
/ RATIO (RATIO = APLL_RATIO + 1)
APLL
and DIV ) must be set to more than 1. For more information
ARM
CLOCK CONTROLLER
DOUT
MPLL, MPLL2,
Reset Value
-
0x1
-
0x1
-
0x0
-
0x0
-
0x0
2.3-35