Samsung S5PC100 User Manual page 440

S5PC100 USER'S MANUAL (REV1.0) ONENAND CONTROLLER
2 FUNCTIONAL DESCRIPTION
2.1 BLOCK DIAGRAM
Figure 5.3-1 OneNAND Controller Block Diagram
2.2 CLOCK CONTROL
The controller has three clock source inputs. Bus system interface gets AHB bus clock, HCLK. Flash controller
core gets two flash clocks, SCLK_ONENAND and SCLK_ONENAND2. Frequency of SCLK_ONENAND should be
double of SCLK_ONENAND2, which is supplied to OneNAND flash memory.
Set the frequency ratio in the SFR of the System Controller. Refer to "Chapter 2.3 Clock Controller" for clock ratio
settings.
If you change the clock frequency ratio, you should follow the below procedure:
5.3-3