Samsung S5PC100 User Manual page 823

S5PC100 USER'S MANUAL (REV1.0)
5.2.7 USB HcHCCA Register (UHCHCCA, Address = 0xED40_0018)
The UHCHCCA register contains the exact physical address of the host controller communication area.
UHCHCCA Bit
HCCA [31:8]
- [7:0]
5.2.8 USB HcPeriodCurrentED Register (UHCPDCURRED, R, Address = 0xED40_001C)
The UHCPDCURRED register contains the exact physical address of the current Isochronous or Interrupt
Endpoint Descriptor. The register organization and individual bit definitions are shown in Table 8.9-9. The lower 4
bits are read as 0 and are unaffected by writes.
UHCPDCURRED
PCED [31:4]
-
Table 8.9-7 UHCHCCA Bit Definitions
Host Controller Communication Area
Base address of the host controller communication area.
This register is a pointer to an area that holds the control
structures and the interrupt table that both the host controller
and the host controller driver access. The minimum
alignment for the HCCA is 256 bytes; therefore, bits 0
through 7 of this register always return 0 if read. Refer to
Chapter 4 of the OHCI Revision. 1.0a Specification.
Fixed at 0
Table 8.9-8 UHCPDCURRED Bit Definitions
Bit
PeriodCurrent Endpoint Descriptor
This register is used by the UHC to point to the head of
one Periodic list which is processed in the current frame.
The content of this register is updated by the UHC after a
Periodic ED has been processed. The HCD reads the
content in determining which ED is currently being
processed at the time of reading. This address is 32 byte
aligned, therefore, the lower 4 bits are always 0
[3:0] Fixed at 0
Description
Description
USB HOST CONTROLLER
R/W Reset Value
R/W
R
R/W Reset Value
R
R
8.9-23