Samsung S5PC100 User Manual page 229

Power Management
7 POWER ON SEQUENCE AND RESET CONTROL
S5PC100 has power-on sequence and four types of resets and reset generator places the system into one of four
reset states.
• Hardware Reset – If XnRESET is driven to low it generates hardware reset. It is an uncompromised, ungated,
total and complete reset that is used if you want to drive S5PC100 to a known initial state due to various
reasons.
• Software Reset – Set special control register to reset signal.
• Watchdog Reset – Reset signal by watchdog timer
• Wakeup Reset – Generates Reset signal if a module that has normal F/Fs is powered down, and the module
is powered up again by wakeup events; but in sleep mode, wakeup reset is generated to all modules that were
powered off regardless of normal F/F or retention F/F.
7.1 POWER ON SEQUENCE
Power-on sequence starts progress after power is supplied to the S5PC100.
Figure 2.4-5 shows the clock behavior during the power-on sequence. The crystal oscillator begins oscillation
within about 2~3 milliseconds after the power supply supplies enough power-level to the S5PC100. Internal PLLs
become disabled after power turns on. XnRESET signal should be released after the fully settle-down of the
power supply-level. For the proper system operation, the S5PC100 requires a hazard-free system clock
(ARMCLK, HCLK and PCLK) when the system reset is released (XnRESET). However, since PLLs are disabled,
Fin (the direct external oscillator clock) is fed directly to HCLK instead of the MPLL_CLK (PLL output) before the
S/W configures the MPLLCON register to enable the operation of PLLs. If new P/M/S values are required, the S/W
configures P/M/S field first, and the PLL_EN field later.
The PLL begins the lockup sequence toward the new frequency only after the S/W configures the PLL with a new
frequency-value. HCLK is configured to be PLL output (MPLL_CLK) immediately after lock time.
Caution: Power regulator for system must be stable prior to the release of XnRESET. Otherwise, it damages to
S5PC100 and its operation is not guaranteed.
S5PC100 has four PLLs namely: APLL, MPLL, EPLL, HPLL.
1. APLL: Used to generate ARM clock
2. MPLL: Used to generate system bus clock and several special clocks
3. EPLL: Used to generate several special clocks
4. HPLL: Used to generate HDMI phy clock
Clock timing constraints are summarized in Table 2.4-13.
2.4-30
S5PC100 USER'S MANUAL (REV1.0)