Samsung S5PC100 User Manual page 577

S5PC100 USER'S MANUAL (REV1.0)
Interrupts
The DMAC provides the irq signals to use as active-high level-sensitive interrupts to external CPUs. If you
program the Interrupt Enable Register to generate an interrupt, after the DMAC executes
corresponding irq HIGH.
You can clear the interrupt by writing to the Interrupt Clear Register.
Following are the steps to control interrupt:
1. Setup the Interrupt Enable Register to generate interrupts.
•
The interrupt enable register is a 32-bit register. Each bit of the INTEN Register controls if the DMAC signals
an interrupt using the corresponding irq.
•
Programs the appropriate bit to control how the DMAC responds if it executes DMASEV:
√
Bit [N] = 0 If executing DMASEV for event N then the DMAC signals event N to all of the threads.
√
Bit [N] = 1 If executing DMASEV for event N then the DMAC sets irq[N] HIGH.
2. Program assembly code to set the corresponding
•
Use DMASEV instruction to signal an interrupt using one of the IRQ outputs.
3. Clear the interrupt by writing to the Interrupt Clear Register
•
Each bit in the INTCLR Register controls the clearing of an interrupt.
•
Program to controls the clearing of the irq outputs:
√
Bit [N] = 0 The status of irq[N] does not change.
√
Bit [N] = 1 The DMAC sets irq[N] LOW.
Interrupt also occurs if DMA is at fault status.
Summary
1. You can configure the DMAC with up to eight DMA channels, with each channel being capable of supporting a
single concurrent thread of DMA operation. In addition there is a single DMA manager thread to initialize the
DMA channel thread.
2. Channel thread
A. Each channel thread does actual DMA operation. You must make assembly code representing your
intention. If you need a number of independent DMA channels, you must make a number of assembly
codes for each.
B. Assemble them, link them into one file, and load it into memory.
3. Start each channel using DBGCMD, DBGINST0, and DBGINST1 SFR.
IRQ HIGH by executing DMASEV.
DMA CONTROLLER
it sets the
DMASEV
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