Samsung S5PC100 User Manual page 329

S5PC100 USER'S MANUAL (REV1.0)
3 ETB
3.1 ABOUT THE ETB
The ETB provides on-chip storage of trace data using 32-bit RAM. Figure 3.2-7 shows the main ETB blocks. The
ETB accepts trace data from CoreSight trace source components through an AMBA Trace Bus (ATB).
The ETB contains the following blocks:
•
Formatter - Inserts source ID signals into the data packet stream so that trace data can be re-associated with
its trace source after the data is read back out of the ETB.
•
Control - Control registers for trace capture and flushing.
•
APB interface - Read, write, and data pointers provide access to ETB registers. In addition, the APB interface
supports wait states through the use of a PREADYDBG signal output by the ETB. The APB interface is
synchronous to the ATB domain.
•
Register bank - Contains the management, control, and status registers for triggers, flushing behavior, and
external control.
•
Trace RAM interface - Controls reads and writes to the Trace RAM.
•
Memory BIST interface - Provides test access to the Trace RAM.
CORESIGHT
3.2-11