Samsung S5PC100 User Manual page 932

MODEM INTERFACE
8 REGISTER DESCRIPTION
Register
0xED50_0000 ~
MSBM
0xED50_3FFC
Register
INT2AP 0xED50_8000
INT2MSM 0xED50_8004
MIFCON 0xED50_8008
MIFPCON 0xED50_800C
MSMINTCLR 0xED50_8010
DMA_TX_ADR 0xED50_8014
DMA_RX_ADR 0xED50_8018
8.1 INTERRUPT REQUEST TO AP REGISTER (INT2AP, R/W, ADDRESS = 0XED50_8000)
INT2AP Bit
Reserved [31:14] Reserved
INT2AP_ADR [13:0]
8.2 INTERRUPT REQUEST TO MODEM REGISTER (INT2MSM, R/W, ADDRESS = 0XED50_8004)
INT2MSM Bit
Reserved [31:14] Reserved
INT2MSM_ADR [13:0]
NOTE: It is recommended that AP writes data with half-word access on the interrupt port because AP overwrites the data
in INT2AP if there are INT2AP and INT2MSM sharing the same word.
8.11-10
Address R/W
R/W
Address R/W
R/W
R/W
R/W Modem Interface Control Register
R/W Modem Interface Port Control register
W
R/W
R/W DMA RX Request Address Register
Modem interface requests the interrupt to AP if modem chip
writes this address. This interrupt is cleared by the interrupt
controller of AP and write access to the MSMINTCLR register.
Modem interface (in this module) requests the interrupt to modem
chip if AP writes this address and clears the interrupt if modem
chip write 1 to the corresponding bit field.
Description
MODEM I/F SRAM Buffer Memory (AP side)
Description
Interrupt Request to AP Register
Interrupt Request to MSM Modem Register
MSM Modem Interface Pending Interrupt
Request Clear
DMA TX Request Address Register
Description
Description
S5PC100 USER'S MANUAL (REV1.0)
Reset Value
Reset Value
0x00003FFE
0x00003FFC
0x00000008
0x00000000
0x17FE_13FE
0x1FFE_1BFE
Reset Value
Reset Value
-
-
0
0x3FFE
0
0x3FFC