Samsung S5PC100 User Manual page 647

S5PC100 USER'S MANUAL (REV1.0)
6.10 UART CHANNEL BAUD RATE DIVISIOR REGISTER
•
UBRDIV0, R/W, Address = 0xEC00_0028
•
UBRDIV1, R/W, Address = 0xEC00_0428
•
UBRDIV2, R/W, Address = 0xEC00_0828
•
UBRDIV3, R/W, Address = 0xEC00_0C28
UBRDIV n
UBRDIVn
NOTE: If UBRDIV value is 0, UART baudrate is not affected by UDIVSLOT value.
6.11 UART CHANNEL DIVIDING SLOT REGISTER
•
UDIVSLOT0, R/W, Address = 0xEC00_002C
•
UDIVSLOT1, R/W, Address = 0xEC00_042C
•
UDIVSLOT2, R/W, Address = 0xEC00_082C
•
UDIVSLOT3, R/W, Address = 0xEC00_0C2C
UDIVSLOT n
UDIVSLOTn [15:0]
Bit
[15:0] Baud rate division value
(When UART clock source is PCLK, UBRDIVn must be more
than 0 (UBRDIVn >0))
Bit
Select the slot where clock generator divide clock source
Description
Description
UART
Reset Value
-
Reset Value
-
8.1-23