Samsung S5PC100 User Manual page 353

S5PC100 USER'S MANUAL (REV1.0) ASYNC BRIDGE
2.2.2 Write Performance
When the master in slow domain burst writes slave in fast domain, the write data FIFO of Async Bridge may
underflow. It causes the fast bus stalling to wait for supplying of slow master's data, and the stalling of data
channel makes bubbles in write data bus. Unfortunately, the write data bubbles cannot be removed by any kind of
DRAM controller. Increasing the write data FIFO size is also useless in this case.
There might be two types of bubbles caused by Async Bridge.
First, the difference of clock speed of master and slaves makes bubbles in write data channel itself. The master
writes down the write data to the write FIFO of Async Bridge in low speed as long as FIFO is not full. The slave
can fetch the write data from write FIFO of Async Bridge in relative high speed as long as WREADY is asserted.
However, the slave's fetching speed is faster than the master's filling speed, after fetching several beat of data,
the slave should wait for the master's writing down. It causes the bubbles in the write data channel.
In S5PC100, in order to avoid the bubble condition, WREADY of Async Bridge's slave part is delayed for proper
cycles according to the clock speed rate of master and slave as shown in Figure 3.4-9.
As shown in Figure 3.4-9, although we delayed the WREADY signal, and it causes delayed reception of write data
to slave, the last write data is not delayed at all. That means, there is no latency penalty with bubble squeezing
scheme.
The size of write data FIFO is also increased to 16 in order to accumulate the write data without FIFO overflow,
when the slave part of Async Bridge wait for delayed WREADY signal.
Master_CLK
Master_AWVALID
Master_WDATA
D0 16burst D1 16burst
Slave_CLK
Slave_WREADY
D0 D0 D0 D0 D1 D1
Slave_WDATA
Delay for squeeze bubbles in Delay for squeeze bubbles in
WDATA channel WDATA channel
Delayed Slave_WREADY
D0 D1
Squeezed Slave_WDATA
Bubbles are squeezed out by delaying assertion of WREADY signal
Figure 3.4-9 Write Data Bubble Squeezing Scheme in Async Bridge
3.4-11